spinqick.models.hardware_config_models

Pydantic templates for hardware config parameters.

Classes

`VoltageSourceType`
`AuxGate`	Auxiliary gate model.
`HemtGate`	Auxiliary gate model specific for powering HEMTs.
`SlowGate`	Model for gates with a DC voltage source channel.
`FastGate`	Model for gates associated with both a DC source channel and qick generator.
`SourceDrainIn`	Model describing the source-drain AC signal into the device.
`SourceDrainOut`	Model describing the output readout signal from the device.
`DacSettings`	Specific settings pertaining to slow speed DACs.
`HardwareConfigBase`	Model for the hardware config in versions < 2.0.2 .
`HardwareConfig`	Model for the full hardware config.

Module Contents

class spinqick.models.hardware_config_models.VoltageSourceType

slow_dac = 'slow_dac'

test = 'test'

class spinqick.models.hardware_config_models.AuxGate

Bases: pydantic.BaseModel

Auxiliary gate model.

slow_dac_address: str

slow_dac_channel: int

class spinqick.models.hardware_config_models.HemtGate

Bases: AuxGate

Auxiliary gate model specific for powering HEMTs.

dc_conversion_factor: float

max_v: float

sd_out: int

class spinqick.models.hardware_config_models.SlowGate

Bases: pydantic.BaseModel

Model for gates with a DC voltage source channel.

dc_conversion_factor: float

slow_dac_address: str

slow_dac_channel: int

max_v: float

gate_type: spinqick.helper_functions.spinqick_enums.GateTypes

crosscoupling: Dict[spinqick.helper_functions.spinqick_enums.GateNames, float] | None = None

class spinqick.models.hardware_config_models.FastGate

Bases: SlowGate

Model for gates associated with both a DC source channel and qick generator.

dac_conversion_factor: float

qick_gen: int

class spinqick.models.hardware_config_models.SourceDrainIn

Bases: pydantic.BaseModel

Model describing the source-drain AC signal into the device.

qick_gen: int

unit_conversion: float

sd_units: str

class spinqick.models.hardware_config_models.SourceDrainOut

Bases: pydantic.BaseModel

Model describing the output readout signal from the device.

qick_adc: int

unit_conversion: float

adc_units: str

class spinqick.models.hardware_config_models.DacSettings

Bases: pydantic.BaseModel

Specific settings pertaining to slow speed DACs.

t_min_slow_dac: float = 3.0

trig_length: float = 0.2

trig_pin: int = 0

class spinqick.models.hardware_config_models.HardwareConfigBase

Bases: pydantic.BaseModel

Model for the hardware config in versions < 2.0.2 .

sd_in: SourceDrainIn

m1_readout: List[SourceDrainOut]

m2_readout: List[SourceDrainOut]

rf_gen: int | None = None

rf_trig_pin: int | None = None

ac_gate: SourceDrainIn | None = None

channels: Dict[spinqick.helper_functions.spinqick_enums.GateNames, FastGate | SlowGate | HemtGate | AuxGate]

voltage_source: Literal['test', 'slow_dac'] | None = 'test'

class spinqick.models.hardware_config_models.HardwareConfig

Bases: HardwareConfigBase

Model for the full hardware config.

dac_settings: DacSettings